A MOSFET device, amongst other features, has a metal oxide capacitor, consisting of a gate and gate oxide layer. In such a device, the gate oxide material is layered underneath the gate spanning between the source and the drain region of the device. The dielectric constant k of the gate oxide material and the thickness d of the gate oxide layer determine the capacitance and field homogeneity and thus the device performance. Damage to the gate oxide layer during the manufacturing process may result in either device failure or at minimum, in an undesired reduction of device performance. Therefore, in order to achieve satisfactory device performance, the gate oxide layer should remain intact during manufacture of the semiconductor device.
In conventional processes, a MOSFET precursor comprises a substrate, e.g., a silicon-on-insulator (SOI) region. A layer of gate oxide is deposited onto the entire wafer surface. In a subsequent step, a polysilicon gate is fabricated, in conventional manners, at a desired location over the gate oxide layer. At this stage and prior to etching the source and drain region, the polysilicon gate is protected by silicon nitride at its sidewalls and top surface, e.g., a nitride sidewall and cap, respectively. The nitride sidewall and cap layers are typically very thick, in the ranges of upwards of 20 nm. Once the nitride sidewall and cap layers are formed, the source and drain regions are etched by anisotropic methods such as reactive ion etching (RIE). This results in the structure comprising a polysilicon gate with the thick nitride sidewall and cap layer, and the underlying gate oxide layer that is laterally exposed to the source and drain wells.
Prior to filling the source and drain wells with epitaxial material, the wells undergo an isotropic cleaning to remove any native oxide material that was generated during the previous steps, e.g., etching of the wells. During this so-called EPI pre-clean step, the oxide material is treated with hydrogen fluoride or similar reagents to generate volatile reaction products. After removal of the volatile products, the surface of the source and drain region comprises pure silicon which serves as basis for growth of the epitaxial material of the source and drain region.
However, the isotropic EPI pre-clean step also etches away unprotected areas of the gate oxide layer. That is, during the EPI pre-clean, the gate oxide layer is subject to the removal reagents which removes portions of the gate oxide layer, resulting in an undercut of up to 5 nm or more under the gate. This effectively shortens the length of the gate oxide layer and exposes portions of the gate. Prior to removing the nitride sidewall, the wells are filled to form the source and drain region. The material, which is used to fill the source and drain, will also fill the undercut region and hence come into direct contact with the gate.
Thus, if the gate oxide is undercut too much, the material for filling the source and drain region will come into contact with the gate, itself. This will result in failure of the device. Accordingly, to avoid device failure, in conventional device manufacture, the protective sidewalls are 10 nm or thicker to ensure that the undercut, during the cleaning process, does not corrode the gate oxide to such an extent that the gate becomes exposed in the undercut. However, due to the thickness of the sidewalls, i.e., 10 nm or greater, the conventional device has a source well to drain well distance greater than the actual gate length, thus ensuring that there will be no shorting but also negatively affecting device performance.